module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);

	localparam IDLE=3'b000;
	localparam S1=3'b001;//*
	localparam S2=3'b010;//1
	localparam S3=3'b011;//11
	localparam S4=3'b100;//111
	localparam S5=3'b101;//1111,
	localparam S6=3'b110;//11110,forever
	
	reg reset_s;
	reg [2:0]state;
	reg [2:0]next_state;
	always@(posedge clk)begin
		if(reset&reset_s)begin
			state<=IDLE;
		end
		else begin
			state<=next_state;
		end
	end
	
	always@(*)begin
		case(state)
			IDLE:begin
				next_state=S1;
				reset_s=1'b0;
			end
			S1:begin
				next_state=(reset)?S1:S2;
				reset_s=1'b0;
			end
			S2:begin//1
				next_state=S3;
				reset_s=1'b1;
			end
			S3:begin//11
				next_state=S4;
				reset_s=1'b1;
			end
			S4:begin//111
				next_state=S4;
				reset_s=1'b1;
			end
			S5:begin//1111,forever
				next_state=S5;
				reset_s=1'b1;
			end
			S6:begin
				next_state=S6;
				reset_s=1'b1;
			end
			default:begin
				next_state=next_state;
				reset_s=reset_s;
			end
		endcase
	end
//assign shift_ena=state==S1|state==S2|state==S3|state==S4|state==S5;
assign shift_ena=state!=S5;
	
endmodule